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| Ordering number : EN8317 Monolithic Digital IC LB11876 Overview For Polygonal Mirror Motors Three-Phase Brushless Motor Driver The LB11876 is a 3-phase brushless motor driver developed for driving the polygonal mirror motor in plain-paper copiers and similar products. It can support any motor voltage and motor current required by the use of appropriate external components. The LB11876 adopts direct PWM drive to achieve drive with minimal power loss. Functions * This is a version of the LB11875 with a modified constraint protection function. * Three-phase bipolar drive (direct PWM) * PLL speed control circuit * Dedicated external clock * Clock divider switching function * Hall sensor FG support * Short-circuit braking function * Built-in current limiter, thermal protection, constraint protection, and undervoltage protection circuits Specifications Absolute Maximum Ratings at Ta = 25C Parameter Supply voltage Input current Output current LVSD pin apply voltage Symbol VCC max I13 max IO max LVSD max V13 pin UL pin, VL pin, WL pin, UH pin, VH pin, and WH pin Conditions Ratings 18 5 30 Unit V mA mA V 18 Continued on next page. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. 41807 TI PC B8-8869 No.8317-1/15 LB11876 Continued from preceding page. Parameter Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature *1 Specified circuit board : 114.3 x 76.1 x Symbol Pd max1 Pd max2 Topr Tstg 1.6mm3, glass epoxy. Independent IC When mounted on a circuit board *1 Conditions Ratings 0.62 1.36 -20 to +80 -55 to +150 Unit W W C C Allowable Operating Ranges at Ta = 25C Parameter Supply voltage range 1 Supply voltage range 2 Input current range Output current 5V constant voltage output LD pin apply voltage LD pin output current FGS pin apply voltage FGS pin output current Symbol VCC1 VCC2 I13 IO IREG VLD ILD VFGS IFGS With VCC shorted to VREG V13 pin UL pin, VL pin, WL pin, UH pin, VH pin, and WH pin Conditions Ratings 8 to 17 4.5 to 5.5 0.5 to 4 20 0 to -30 0 to 17 0 to 15 0 to 17 0 to 10 Unit V V mA mA mA V mA V mA Electrical Characteristics at Ta = 25C, VCC = 12V Parameter Supply current 1 Supply current 2 Symbol ICC1 ICC2 Stop mode Conditions min Ratings typ 15 3 max 25 5 mA mA Unit 5V constant voltage output (VREG pin) Output voltage Line regulation Load regulation Temperature coefficient VREG VREG1 VREG2 VREG3 VCC = 8 to 13.5V IO = 0 to -15mA Design target 4.65 5.0 40 20 0 5.35 100 100 V mV mV mV/C 13V constant voltage output (V13 pin) Output voltage Output Block Output saturation voltage 1-1 Output saturation voltage 1-2 Output saturation voltage 2 Output leakage current Hall Sensor Amplifier Block Input bias current Common-mode input voltage range1 Common-mode input voltage range2 Input sensitivity Hysteresis Input current low high Input current high low FG Schmitt Trigger Block Input bias current Common-mode input voltage range1 Common-mode input voltage range2 Input sensitivity Hysteresis Input current low high Input current high low VIN (FGS) VIN (FGS) VSLH (FGS) VSHL (FGS) VICM2 (FGS) When a single-sided input bias is used (using a Hall sensor IC) Sine wave Design target Design target Design target 80 15 24 12 -12 42 mVp-p mV mV mV Continued on next page. 0 VCC V IB (FGS) VICM1 (FGS) When a Hall sensor is used -2 0.5 -0.5 VCC - 2.0 A V VIN (HA) VSLH (HA) VSHL (HA) VICM2 (HA) When a single-sided input bias is used (using a Hall sensor IC) Sine wave 80 15 24 12 -12 42 mVp-p mV mV mV 0 VCC V IHB (HA) VICM1 (HA) When a Hall sensor is used -2 0.5 -0.5 VCC - 2.0 A V VO sat1-1 VO sat1-2 VO sat2 IO leak Low level, IO = 400A Low level, IO = 10mA High level, IO = -20mA VCC - 1.2 0.2 0.9 VCC - 0.9 10 0.5 1.2 V V V A V13 IO = 2mA 12.5 13.5 14.5 V No.8317-2/15 LB11876 Continued from preceding page. Parameter FGS Output Output saturation voltage Output leakage current PWM Oscillator High-level output voltage Low-level output voltage External capacitor charge current Oscillator frequency Amplitude CSD Oscillator Circuit High-level output voltage Low-level output voltage External capacitor charge current External capacitor discharge current Oscillator frequency Amplitude Phase Comparator Output High-level input voltage Low-level input voltage Input source current Input sink current Phase Lock Detection Output Output saturation voltage Output leakage current Error Amplifier Block Input offset voltage Input bias current High-level output voltage Low-level output voltage DC bias level Current Llimiter Circuit Llimiter voltage Low Voltage Protection Circuit Operating voltage Release voltage Hysteresis Thermal shutdown circuit Thermal shutdown operating temperature Thermal shutdown temperature hysteresis CLD Circuit External capacitor discharge current Operating voltage VH (CLD) 3.25 3.5 3.75 V Continued on next page. ICLD -5 -4 -3 A TSD TSD Design target value (junction temperature) Design target value (junction temperature) 30 C 150 180 C VSDL VSDH VSD 3.5 4.0 0.35 3.7 4.2 0.5 3.9 4.4 0.65 V V V VRF 0.225 0.25 0.275 V VIO (ER) IB (ER) VOH (ER) VOL (ER) VB (ER) IEI = -0.1mA, no load IEI = 0.1mA, no load Design target value -5% Design target value -10 -0.4 3.7 1.3 VREG/2 5% 10 0.4 mV A V V V VOL( LD) IL (LD) ILD = 10mA VO = VCC 0.15 0.4 10 V A VPDH VPDL IPD+ IPDIOH = -100A IOH = 100A VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.2 VREG - 0.1 0.2 0.3 -0.6 V V mA mA f (CSD) V (CSD) C = 0.068F 2.2 30 2.4 2.6 Hz Vp-p ICHG2 7 10 13 A VOH (CSD) VOL (CSD) ICHG1 3.2 0.9 -13 3.5 1.1 -10 3.8 1.3 -7 V V A f (PWM) V (PWM) C = 620pF 1.0 50 1.2 1.4 kHz Vp-p VOH (PWM) VOL (PWM) ICHG VPWM = 2.0V 2.6 1.4 -65 2.9 1.7 -50 3.2 2.0 -35 V V A VOL (FGS) IL (FGS) ILD = 7mA VO = VCC 0.15 0.5 10 V A Symbol Conditions min Ratings typ max Unit No.8317-3/15 LB11876 Continued from preceding page. Parameter CLKIN pin External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current S/S pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current F/R pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current BRSEL pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current CLKSEL pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current VIH (CSEL) VIL (CSEL) VIO (CSEL) VIS (CSEL) IIH (CSEL) IIL (CSEL) VCSEL = VREG VCSEL = 0V 2.0 0 VREG - 0.5 0.13 -10 -130 0.21 0 -90 0.29 10 V A A VREG 1.0 VREG V V V VIH (BSEL) VIL (BSEL) VIO (BSEL) VIS (BSEL) IIH (BSEL) IIL (BSEL) VBSEL = VREG VBSEL = 0V 2.0 0 VREG - 0.5 0.13 -10 -130 0.21 0 -90 0.29 10 V A A VREG 1.0 VREG V V V VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) VF/R = VREG VF/R = 0V 2.0 0 VREG - 0.5 0.13 -10 -130 0.21 0 -90 0.29 10 V A A VREG 1.0 VREG V V V VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VS/S = VREG VS/S = 0V 2.0 0 VREG - 0.5 0.13 -10 -130 0.21 0 -90 0.29 10 V A A VREG 1.0 VREG V V V fI (CKIN) VIH (CKIN) VIL (CKIN) VIO (CKIN) VIS (CKIN) IIH (CKIN) IIL (CKIN) VCKIN = VREG VCKIN = 0V 0.1 2.0 0 VREG - 0.5 0.13 -10 -130 0.21 0 -90 0.29 10 V A A 10 VREG 1.0 VREG kHz V V V Symbol Conditions min Ratings typ max Unit No.8317-4/15 LB11876 Package Dimensions unit : mm (typ) 3247A 2.0 Pd max - Ta 36 19 Allowable power dissipation, Pd max - W 1.5 5.6 0.5 7.6 1.36W Specified circuit board : 114.3x76.1x1.6mm3 glass epoxy board 1 0.3 18 0.2 1.0 0.62W 0.5 Independent IC 0.761W 15.0 1.7max (1.5) 0.347W 0 - 20 0 20 40 60 80 100 SANYO : SSOP36(275mil) Three-Phase Logic Truth Table (The input "H" state is the state where IN+ > IN-) F/R= "L" IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R ="H" IN2 H H L L L H IN3 L H H H L L Output Source VH WH WH UH UH VH Sink UL UL VL VL WL WL S/S pin Input state High or open Low State Stop Start 0.1 (0.7) 0.8 Ambient temperature, Ta - C BRSEL pin Input state High or open Low During deceleration Free running Short-circuit braking CLKSEL pin Input state High or open Low Clock divisor 1 2 fFG = fCLK / divisor No.8317-5/15 LB11876 Pin Assignment RFGND FGIN+ FGIN- IN1+ IN2+ IN3+ GND 20 17 V13 5k 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 19 LB11876 1 CLK 2 FGS 3 LD 4 S/S 5 CLKSEL 6 BRSEL 7 F/R 8 PD 9 EI 10 EO 11 TOC 12 NC 13 PWM 14 CLD 15 CSD 16 VREG 18 LVSD 1 2 3 No.8317-6/15 Top view Pin Functions Pin No. 1 Pin CLK Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. Hysteresis : about 0.21V f = 10kHz (maximum) Description External clock signal input Equivalent Circuit VREG 50k 2 FGS FG Schmitt trigger output This is an open-collector output. VREG 3 LD Phase lock detection output This output goes to the on state (low-level output) in the phase locked state. This is an open-collector output. VREG Continued on next page. VCC IN1- IN2- IN3- UH WH VH WL UL VL RF LB11876 Continued from preceding page. Pin No. 4 Pin S/S Start/stop control Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. A low level specifies the start state. Hysteresis : about 0.21V Description Equivalent Circuit VREG 50k 5k 4 5 CLK SEL Clock divisor selection Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. A low level specifies a divisor of two, and a high level specifies a divisor of 1. Hysteresis : about 0.21V VREG 50k 5k 5 6 BR SEL Deceleration (braking) control selection Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. A low level specifies short-circuit braking, and a high level or open specifies free running operation. Hysteresis : about 0.21V VREG 50k 5k 6 7 F/R Forward/reverse selection Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. A low level specifies forward operation. Hysteresis : about 0.21V VREG 50k 5k 7 Continued on next page. No.8317-7/15 LB11876 Continued from preceding page. Pin No. 8 Pin PD Description Phase comparator output The phase error is converted to a pulse duty and output from this pin. Equivalent Circuit VREG 8 9 EI Error amplifier input VREG 300 9 10 EO Error amplifier output VREG 10 40k 11 TOC Torque command input This pin is normally connected to the EO pin. When the TOC voltage falls, the UH, VH, and WH on duty is increased. VREG 200 11 12 NC Since this pin is not connected to any internal circuits, it may be used as a connection point. Continued on next page. No.8317-8/15 LB11876 Continued from preceding page. Pin No. 13 Pin PWM Description Sets the PWM oscillator frequency. Connect a capacitor between this pin and ground. A 620pF capacitor sets the oscillator frequency to be about 50kHz. Equivalent Circuit VREG 200 13 1k 14 CLD Phase lock signal mask time setting A mask time of about 90ms can be set up by connected a capacitor (about 0.1F) between this pin and ground.Leave this pin open if there is no need to mask the phase lock signal. VREG 300 14 15 CSD Constraint protection circuit operating time setting and initialization pulse setting A protection circuit operating time of about 1 seconds can be set up by connecting a capacitor (about 0.068F) between this pin and ground. Connect both a capacitor and a resistor (about 220k and 4700pF) in parallel between this pin and ground if this protection circuit is not used. VREG Reset circuit 300 15 16 VREG Stabilized power supply output (5V output) Connect a capacitor between this pin and ground for power supply stabilization. (About 0.1F) VREG 16 Continued on next page. No.8317-9/15 LB11876 Continued from preceding page. Pin No. 17 Pin V13 Description 13V shunt regulator output Equivalent Circuit 17 18 LVSD Undervoltage protection detection If a power supply voltage of 5V or over is to be detected, connect a Zener diode in series to set the detection voltage. VCC 18 19 20 21 VCC GND RF GND Power supply. Connect a capacitor between this pin and ground for power supply stabilization. Ground Output current detection reference The external resistor Rf is connected to ground. VREG 21 22 RF Output current detection A resistor is connected between RF and ground. The maximum output current IOUT is determined by the equation IOUT = 0.25/Rf. VREG 22 Continued on next page. No.8317-10/15 LB11876 Continued from preceding page. Pin No. 23 24 25 26 27 28 Pin WH WL VH VL UH UL Description Outputs (that drive external transistors) Duty control is applied to the UH, VH, and WH outputs. Equivalent Circuit VCC 23 24 25 50k 26 27 28 29 30 31 32 33 34 IN3IN3+ IN2IN2+ IN1IN1+ Hall sensor inputs "H" is the state where IN+ > IN-, and "L" is the reverse state. If noise on the Hall sensor signals is a problem, connect capacitors between the IN+ and IN- inputs. VCC 500 30 32 34 500 29 31 33 35 36 FGINFGIN+ FG input If noise on the FG signal is a problem, the input signal can be filtered with a capacitor or a capacitor plus resistor. VCC 500 35 500 36 No.8317-11/15 LB11876 Internal Equivalent Circuit Block Diagram and External Reference Circuit (Application example) Hall sensor, FET output 24V single supply VREG CLD LD PD EI LD mask FGINFGIN+ + FG filter LD VREG + FGS FGS EO TOC CLKSEL CLK SEL PLL LVSD 1/2 DEV CLK CLK COMP V13 PWM PWM OSC VREG S/S UL F/R PRI BRSEL BR SEL CSD OSC Logic Hall sensor logic driver UH VL VH WL WH CURR LIM VCC VREG S/S V13 LVSD TSD 24V F/R CSD Hall sensor hysteresis amplifier RF IN1+ IN1- IN2+ IN2- IN3+ IN3- GND RFGND VCC No.8317-12/15 LB11876 LB11876 Overview 1. Speed control circuit Since the LB11876 adopts PLL speed control, it provides precise, low-jitter, and stable motor operation. This PLL circuit compares the falling edge of the CLK signal with the FG signal (the falling edges of the FGIN+ or FGS output) and controls motor operation based on the difference. The FG servo frequency during this control operation is controlled by the frequency given by the following formula which is based on the divisor selected by the clock input frequency (fCLK) and the CLKSEL pin. fFG (servo) = fCLK / No.8317-13/15 LB11876 8. Constraint protection circuit The LB11876 includes a built-in constraint protection circuit to protect the IC and the motor if the motor is physically constrained from turning. If one Hall sensor input signals do not switch states for a period in excess of a certain fixed time in the start state, the PWM drive side output is turned off. The time is set by the capacitor connected to the CSD pin. Set time (seconds) 15.4 x C (F) If a 0.068F capacitor is used, the protection time will be about 1.05 seconds. (If one Hall sensor input signal period becomes longer than this time, the PWM drive side output is turned off.) This set time must have a certain amount of margin with respect to the motor startup time. This protection circuit will not operate during deceleration due to switching the clock frequency. The constraint protection state can be cleared by either switching to the stop state or turning the power off and then on again. Since the CSD pin also functions as the initial reset pulse generation pin, connecting this pin to ground will reset the logic circuits and make speed control operation impossible. Therefore, if the constraint protection circuit is not used, this pin must be connected to ground by a resistor of about 220k and a capacitor of about 4700pF connected in parallel. 9. Undervoltage protection circuit The LB11876 includes a undervoltage protection circuit to prevent incorrect operation when power is first applied or when the power supply voltage falls. The LVSD pin turns the PWM drive side output off at voltages under about 3.7V (typical), and clears the protection state when the voltage rises above about 4.2V (typical). An arbitrary operating voltage can be set by adding an external Zener diode. Note that the maximum applied voltage for the LVSD pin is 18V. 10. Phase lock signal (1) Phase lock range : Since this IC does not have a speed system counter, the speed error range in the phase locked state cannot be determined by the IC characteristics alone. (This is because the range is affected by the acceleration with changes in the FG frequency.) If it is necessary to stipulate this in conjunction with a motor, it will be necessary to measure the range with the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the lock pull-in time at startup and the unlock time due to clock switching will be the cases where the speed error is the largest. (2) Phase lock signal mask function : It is possible to assure that the lock signal is output in stable states by masking the short-term low levels due to hunting during lock pull-in. Note, however, that the lock signal output will be delayed by the amount of the mask time. The mask time is set by the capacitor connected between the CLD pin and ground. Mask time (seconds) 0.9 x C (F) When a 0.1F capacitor is used, the mask time will be about 90ms. If full masking is required, the mask time must be set with an adequate margin. Leave the CLD pin open if masking is not required. 11. Power supply stabilization (1) VCC : Since this IC is used in switching drive applications with large output currents, the power supply line is easily disrupted. Therefore it is necessary to connect an adequately large capacitor between the VCC pin and ground. The capacitor ground side should be located as close to the IC GND pin as possible. Since the power supply line is most easily disrupted during lock pull-in at high speeds, designers must analyze this case carefully and select an adequately large capacitor. Since the power supply line is particularly susceptible to disruption if a diode is inserted in the power supply line to prevent destruction of the IC by reverse connection, an even larger capacitor must be selected in this case. (2) 13V regulator : When implementing a motor driver circuit with single-voltage power supply specifications and a voltage that is outside the power supply voltage range of this IC, the supply voltage required by this IC (approx. 13V) can be created using the V13 pin. The V13 pin circuit is a shunt regulator and can generate a 13V level by supplying current through an external resistor. A stabilized voltage is generating by setting the current to a level in the range 0.5mA to 4mA. An external transistor with a current capacity of over 80mA (ICC + Hall sensor bias current + output source current) and a voltage handling capacity higher than the motor supply voltage must be selected. Since heat generation in the transistor may become a problem, heat dissipation must be provided by the package. (3) 5V regulator : Connect a capacitor with a value over 0.1F to stabilize the VREG voltage, which is the IC's control circuit power supply. That capacitor's ground side must be connected as close as possible to the IC ground. No.8317-14/15 LB11876 12. Power saving circuit This IC goes into a power saving state in which current drain is reduced when set to the stop state. This power saving state is implemented by cutting the bias current to most of the circuits in the IC. The 5V regulator output, however, is still output when the IC is in the power saving state. 13. Error amplifier system components The external components for the error amplifier block must be located as close as possible to the IC to minimize the influence of noise. These components must also be located as far from the motor as possible. 14. Forward/reverse switching In principle, forward/reverse switching must be performed with the motor in the stopped state. This IC does provide circuit workarounds for handling the through currents that occur during switching if the direction is switched while the motor is turning. However, care is required with respect to lifting of the motor supply voltage during this switching, since the motor current will return to the power supply during brief instants. If this becomes a problem, the size of the capacitor connected between the power supply line and ground must be increased. If the motor current after switching exceeds the current limit value, the PWM drive side output will be turned off. However, the opposite side output will go to the short-circuit braking state and a current determined by the motor induced voltage and the coil resistance. This current must be held under the current rating of the output transistors used. (This aspect requires more care the faster the motor speed at which forward/reverse switching occurs.) 15. Brake switching Either free running or short-circuit braking can be selected with the BRSEL pin. The short-circuit braking mode adopts a form in which all phases of the PWM drive side output transistors are turned on (all phases of the reverse side transistors are turned off). Care is required, since the current limiter function does not operate during braking. During braking, the output circuits go to a shorted state with 100% duty. The current that flows in the output transistors during braking is determined by the motor induced voltage and the coil resistance. This current must be held under the current rating of the output transistors used. (This aspect requires more care the faster the motor speed at which braking occurs.) 16. NC pins Since the NC pins are electrically open, they can be used for intermediate wiring connections without problem. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2007. Specifications and information herein are subject to change without notice. PS No.8317-15/15 |
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